-- Copyright (c) 2010, Pavel Kovar
-- All rights reserved.
--
---------------------------------------------------------------------------------------
-- This file is a part of the Witch Navigator project

-- WitchNav Top
-- Implemented
--   * building blocks interconnection
--   * ExpressCard auxiliary signals


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity WitchNavTop is
PORT(
	-- clk & rst
        clk_20M : in std_logic; -- only used in cor_top in order to generate clk_dsp
	pci_reset : in std_logic;
	clkreq : out std_logic;
	pcie_weak : out std_logic;
	
	pci_clkp : in std_logic;
	pci_clkn : in std_logic;
	
	-- I2C
   sda : inout  STD_LOGIC;
   scl : inout  STD_LOGIC;
	
	-- PCIe
	pci_exp_txp : out std_logic;
   pci_exp_txn : out std_logic;
   pci_exp_rxp : in  std_logic;
   pci_exp_rxn : in  std_logic;
	
   -- ADC
	s1_in : in std_logic_vector(7 downto 0);
	s2_in : in std_logic_vector(7 downto 0);
	agc1  : out std_logic;
	agc2	: out std_logic;
	clk_adc : out std_logic;
	
	-- LEDs
	led_1 : out std_logic;
	led_2 : out std_logic);
	
end WitchNavTop;

architecture Behavioral of WitchNavTop is
	
	-- i2c
	signal i2ccontrol, i2cstatus : std_logic_vector(31 downto 0);
	-- mem
	signal mem_wr_we : std_logic_vector(3 downto 0);
	signal mem_wr_data : std_logic_vector(31 downto 0);
	signal mem_wr_addr : std_logic_vector(19 downto 0);
	signal mem_rd_data : std_logic_vector(31 downto 0);
	signal mem_rd_ce : std_logic;
	signal mem_rd_addr : std_logic_vector(19 downto 0);
	signal mem_clk : std_logic;
	
	-- PCIe
	signal tic_int : std_logic;
	signal tic_int_en : std_logic;
	signal pcie_rst_n : std_logic;
	signal trn_reset_n : std_logic;
	signal received_hot_reset : std_logic;
	signal dma_wr_addr : std_logic_vector(31 downto 0);
	signal dma_ctrl : std_logic;
	
	    -- Transaction (TRN) Interface
    signal trn_lnk_up_n            : std_logic;
	 signal trn_clk					  : std_logic;
	 
    -- Tx
    signal trn_td                  : std_logic_vector(31 downto 0);
    signal trn_tsof_n              : std_logic;
    signal trn_teof_n              : std_logic;
    signal trn_tsrc_rdy_n          : std_logic;
    signal trn_tdst_rdy_n          : std_logic;
    signal trn_terr_drop_n         : std_logic;
    signal trn_tsrc_dsc_n          : std_logic;
    signal trn_terrfwd_n           : std_logic;
    signal trn_tbuf_av             : std_logic_vector(5 downto 0);
    signal trn_tstr_n              : std_logic;
    signal trn_tcfg_req_n          : std_logic;
    signal trn_tcfg_gnt_n          : std_logic;

    -- Rx
    signal trn_rd                  : std_logic_vector(31 downto 0);
    signal trn_rsof_n              : std_logic;
    signal trn_reof_n              : std_logic;
    signal trn_rsrc_rdy_n          : std_logic;
    signal trn_rsrc_dsc_n          : std_logic;
    signal trn_rdst_rdy_n          : std_logic;
    signal trn_rerrfwd_n           : std_logic;
    signal trn_rnp_ok_n            : std_logic;
    signal trn_rbar_hit_n          : std_logic_vector(6 downto 0);
    signal trn_fc_sel              : std_logic_vector(2 downto 0);
    signal trn_fc_nph              : std_logic_vector(7 downto 0);
    signal trn_fc_npd              : std_logic_vector(11 downto 0);
    signal trn_fc_ph               : std_logic_vector(7 downto 0);
    signal trn_fc_pd               : std_logic_vector(11 downto 0);
    signal trn_fc_cplh             : std_logic_vector(7 downto 0);
    signal trn_fc_cpld             : std_logic_vector(11 downto 0);

    -- Host (CFG) Interface
    signal cfg_do                  : std_logic_vector(31 downto 0);
    signal cfg_rd_wr_done_n        : std_logic;
    signal cfg_dwaddr              : std_logic_vector(9 downto 0);
    signal cfg_rd_en_n             : std_logic;
    signal cfg_err_ur_n            : std_logic;
    signal cfg_err_cor_n           : std_logic;
    signal cfg_err_ecrc_n          : std_logic;
    signal cfg_err_cpl_timeout_n   : std_logic;
    signal cfg_err_cpl_abort_n     : std_logic;
    signal cfg_err_posted_n        : std_logic;
    signal cfg_err_locked_n        : std_logic;
    signal cfg_err_tlp_cpl_header  : std_logic_vector(47 downto 0);
    signal cfg_err_cpl_rdy_n       : std_logic;
    signal cfg_interrupt_n         : std_logic;
    signal cfg_interrupt_rdy_n     : std_logic;
    signal cfg_interrupt_assert_n  : std_logic;
    signal cfg_interrupt_do        : std_logic_vector(7 downto 0);
    signal cfg_interrupt_di        : std_logic_vector(7 downto 0);
    signal cfg_interrupt_mmenable  : std_logic_vector(2 downto 0);
    signal cfg_interrupt_msienable : std_logic;
    signal cfg_turnoff_ok_n        : std_logic;
    signal cfg_to_turnoff_n        : std_logic;
    signal cfg_pm_wake_n           : std_logic;
    signal cfg_pcie_link_state_n   : std_logic_vector(2 downto 0);
    signal cfg_trn_pending_n       : std_logic;
    signal cfg_dsn                 : std_logic_vector(63 downto 0);
    signal cfg_bus_number          : std_logic_vector(7 downto 0);
    signal cfg_device_number       : std_logic_vector(4 downto 0);
    signal cfg_function_number     : std_logic_vector(2 downto 0);
    signal cfg_status              : std_logic_vector(15 downto 0);
    signal cfg_command             : std_logic_vector(15 downto 0);
    signal cfg_dstatus             : std_logic_vector(15 downto 0);
    signal cfg_dcommand            : std_logic_vector(15 downto 0);
    signal cfg_lstatus             : std_logic_vector(15 downto 0);
    signal cfg_lcommand            : std_logic_vector(15 downto 0);

	-- clk
	signal clk_125 : std_logic;
	signal pll_locked : std_logic;
	signal clk_dsp : std_logic;


	COMPONENT PCIeIIP
	PORT(
		mem_rd_data : IN std_logic_vector(31 downto 0);
		dma_start : IN std_logic;
		dma_addr : IN std_logic_vector(31 downto 0);
		int_dma_enable : IN std_logic;
		trn_clk : IN std_logic;
		trn_reset_n : IN std_logic;
		trn_lnk_up_n : IN std_logic;
		trn_fc_cplh : IN std_logic_vector(7 downto 0);
		trn_fc_cpld : IN std_logic_vector(11 downto 0);
		trn_fc_nph : IN std_logic_vector(7 downto 0);
		trn_fc_npd : IN std_logic_vector(11 downto 0);
		trn_fc_ph : IN std_logic_vector(7 downto 0);
		trn_fc_pd : IN std_logic_vector(11 downto 0);
		trn_tbuf_av : IN std_logic_vector(5 downto 0);
		trn_tcfg_req_n : IN std_logic;
		trn_terr_drop_n : IN std_logic;
		trn_tdst_rdy_n : IN std_logic;
		trn_rd : IN std_logic_vector(31 downto 0);
		trn_rsof_n : IN std_logic;
		trn_reof_n : IN std_logic;
		trn_rsrc_rdy_n : IN std_logic;
		trn_rsrc_dsc_n : IN std_logic;
		trn_rerrfwd_n : IN std_logic;
		trn_rbar_hit_n : IN std_logic_vector(6 downto 0);
		cfg_do : IN std_logic_vector(31 downto 0);
		cfg_rd_wr_done_n : IN std_logic;
		cfg_err_cpl_rdy_n : IN std_logic;
		cfg_interrupt_rdy_n : IN std_logic;
		cfg_interrupt_do : IN std_logic_vector(7 downto 0);
		cfg_interrupt_mmenable : IN std_logic_vector(2 downto 0);
		cfg_interrupt_msienable : IN std_logic;
		cfg_to_turnoff_n : IN std_logic;
		cfg_bus_number : IN std_logic_vector(7 downto 0);
		cfg_function_number : IN std_logic_vector(2 downto 0);
		cfg_status : IN std_logic_vector(15 downto 0);
		cfg_command : IN std_logic_vector(15 downto 0);
		cfg_dstatus : IN std_logic_vector(15 downto 0);
		cfg_dcommand : IN std_logic_vector(15 downto 0);
		cfg_lstatus : IN std_logic_vector(15 downto 0);
		cfg_lcommand : IN std_logic_vector(15 downto 0);
		cfg_pcie_link_state_n : IN std_logic_vector(2 downto 0);
		cfg_device_number : IN std_logic_vector(4 downto 0);          
		mem_wr_we : OUT std_logic_vector(3 downto 0);
		mem_wr_data : OUT std_logic_vector(31 downto 0);
		mem_wr_addr : OUT std_logic_vector(19 downto 0);
		mem_rd_ce : OUT std_logic;
		mem_rd_addr : OUT std_logic_vector(19 downto 0);
		mem_clk : OUT std_logic;
		trn_fc_sel : OUT std_logic_vector(2 downto 0);
		trn_td : OUT std_logic_vector(31 downto 0);
		trn_tsof_n : OUT std_logic;
		trn_teof_n : OUT std_logic;
		trn_tsrc_rdy_n : OUT std_logic;
		trn_tsrc_dsc_n : OUT std_logic;
		trn_terrfwd_n : OUT std_logic;
		trn_tstr_n : OUT std_logic;
		trn_tcfg_gnt_n : OUT std_logic;
		trn_rdst_rdy_n : OUT std_logic;
		trn_rnp_ok_n : OUT std_logic;
		cfg_dwaddr : OUT std_logic_vector(9 downto 0);
		cfg_rd_en_n : OUT std_logic;
		cfg_err_ur_n : OUT std_logic;
		cfg_err_cor_n : OUT std_logic;
		cfg_err_ecrc_n : OUT std_logic;
		cfg_err_cpl_timeout_n : OUT std_logic;
		cfg_err_cpl_abort_n : OUT std_logic;
		cfg_err_posted_n : OUT std_logic;
		cfg_err_locked_n : OUT std_logic;
		cfg_err_tlp_cpl_header : OUT std_logic_vector(47 downto 0);
		cfg_interrupt_n : OUT std_logic;
		cfg_interrupt_assert_n : OUT std_logic;
		cfg_interrupt_di : OUT std_logic_vector(7 downto 0);
		cfg_turnoff_ok_n : OUT std_logic;
		cfg_pm_wake_n : OUT std_logic;
		cfg_trn_pending_n : OUT std_logic;
		cfg_dsn : OUT std_logic_vector(63 downto 0)
		);
	END COMPONENT;

	COMPONENT cor_top
	PORT(
		clk_in : IN std_logic;
		clk_ctr : IN std_logic;
		s1_in : IN std_logic_vector(7 downto 0);
		s2_in : IN std_logic_vector(7 downto 0);
		inmem_addr : IN std_logic_vector(19 downto 0);
		inmem_we : IN std_logic_vector(3 downto 0);
		inmem_data : IN std_logic_vector(31 downto 0);
		outmem_addr : IN std_logic_vector(19 downto 0);
		outmem_ce : IN std_logic;
		i2c_status : IN std_logic_vector(31 downto 0);
		pcie_rst_n : IN std_logic;          
		clkdsp : OUT std_logic;
		agc1 : OUT std_logic;
		agc2 : OUT std_logic;
		clk_adc : OUT std_logic;
		outmem_data : OUT std_logic_vector(31 downto 0);
		i2c_control : OUT std_logic_vector(31 downto 0);
		tic_out : OUT std_logic;
		dma_wr_addr : OUT std_logic_vector(31 downto 0);
		dma_ctrl : OUT std_logic;
		led_1 : OUT std_logic;
		led_2 : OUT std_logic;
		irq_enable : OUT std_logic
		);
	END COMPONENT;


	COMPONENT i2c_top
	PORT(
		clk : IN std_logic;
		i2c_control : IN std_logic_vector(31 downto 0);    
		sda : INOUT std_logic;
		scl : INOUT std_logic;      
		i2c_status : OUT std_logic_vector(31 downto 0)
		);
	END COMPONENT;

  component PCIe is
  generic (
    TL_TX_RAM_RADDR_LATENCY           : integer    := 0;
    TL_TX_RAM_RDATA_LATENCY           : integer    := 2;
    TL_RX_RAM_RADDR_LATENCY           : integer    := 0;
    TL_RX_RAM_RDATA_LATENCY           : integer    := 2;
    TL_RX_RAM_WRITE_LATENCY           : integer    := 0;
    VC0_TX_LASTPACKET                 : integer    := 14;
    VC0_RX_RAM_LIMIT                  : bit_vector := x"7FF";
    VC0_TOTAL_CREDITS_PH              : integer    := 32;
    VC0_TOTAL_CREDITS_PD              : integer    := 211;
    VC0_TOTAL_CREDITS_NPH             : integer    := 8;
    VC0_TOTAL_CREDITS_CH              : integer    := 40;
    VC0_TOTAL_CREDITS_CD              : integer    := 211;
    VC0_CPL_INFINITE                  : boolean    := TRUE;
    BAR0                              : bit_vector := x"FFF00000";
    BAR1                              : bit_vector := x"00000000";
    BAR2                              : bit_vector := x"00000000";
    BAR3                              : bit_vector := x"00000000";
    BAR4                              : bit_vector := x"00000000";
    BAR5                              : bit_vector := x"00000000";
    EXPANSION_ROM                     : bit_vector := "0000000000000000000000";
    DISABLE_BAR_FILTERING             : boolean    := FALSE;
    DISABLE_ID_CHECK                  : boolean    := FALSE;
    TL_TFC_DISABLE                    : boolean    := FALSE;
    TL_TX_CHECKS_DISABLE              : boolean    := FALSE;
    USR_CFG                           : boolean    := FALSE;
    USR_EXT_CFG                       : boolean    := FALSE;
    DEV_CAP_MAX_PAYLOAD_SUPPORTED     : integer    := 2;
    CLASS_CODE                        : bit_vector := x"050000";
    CARDBUS_CIS_POINTER               : bit_vector := x"00000000";
    PCIE_CAP_CAPABILITY_VERSION       : bit_vector := x"1";
    PCIE_CAP_DEVICE_PORT_TYPE         : bit_vector := x"0";
    PCIE_CAP_SLOT_IMPLEMENTED         : boolean    := FALSE;
    PCIE_CAP_INT_MSG_NUM              : bit_vector := "00000";
    DEV_CAP_PHANTOM_FUNCTIONS_SUPPORT : integer    := 0;
    DEV_CAP_EXT_TAG_SUPPORTED         : boolean    := FALSE;
    DEV_CAP_ENDPOINT_L0S_LATENCY      : integer    := 7;
    DEV_CAP_ENDPOINT_L1_LATENCY       : integer    := 7;
    SLOT_CAP_ATT_BUTTON_PRESENT       : boolean    := FALSE;
    SLOT_CAP_ATT_INDICATOR_PRESENT    : boolean    := FALSE;
    SLOT_CAP_POWER_INDICATOR_PRESENT  : boolean    := FALSE;
    DEV_CAP_ROLE_BASED_ERROR          : boolean    := TRUE;
    LINK_CAP_ASPM_SUPPORT             : integer    := 1;
    LINK_CAP_L0S_EXIT_LATENCY         : integer    := 7;
    LINK_CAP_L1_EXIT_LATENCY          : integer    := 7;
    LL_ACK_TIMEOUT                    : bit_vector := x"0204";
    LL_ACK_TIMEOUT_EN                 : boolean    := FALSE;
    LL_REPLAY_TIMEOUT                 : bit_vector := x"0204";
    LL_REPLAY_TIMEOUT_EN              : boolean    := FALSE;
    MSI_CAP_MULTIMSGCAP               : integer    := 0;
    MSI_CAP_MULTIMSG_EXTENSION        : integer    := 0;
    LINK_STATUS_SLOT_CLOCK_CONFIG     : boolean    := FALSE;
    PLM_AUTO_CONFIG                   : boolean    := FALSE;
    FAST_TRAIN                        : boolean    := FALSE;
    ENABLE_RX_TD_ECRC_TRIM            : boolean    := FALSE;
    DISABLE_SCRAMBLING                : boolean    := FALSE;
    PM_CAP_VERSION                    : integer    := 3;
    PM_CAP_PME_CLOCK                  : boolean    := FALSE;
    PM_CAP_DSI                        : boolean    := FALSE;
    PM_CAP_AUXCURRENT                 : integer    := 0;
    PM_CAP_D1SUPPORT                  : boolean    := TRUE;
    PM_CAP_D2SUPPORT                  : boolean    := TRUE;
    PM_CAP_PMESUPPORT                 : bit_vector := x"0F";
    PM_DATA0                          : bit_vector := x"00";
    PM_DATA_SCALE0                    : bit_vector := x"0";
    PM_DATA1                          : bit_vector := x"00";
    PM_DATA_SCALE1                    : bit_vector := x"0";
    PM_DATA2                          : bit_vector := x"00";
    PM_DATA_SCALE2                    : bit_vector := x"0";
    PM_DATA3                          : bit_vector := x"00";
    PM_DATA_SCALE3                    : bit_vector := x"0";
    PM_DATA4                          : bit_vector := x"00";
    PM_DATA_SCALE4                    : bit_vector := x"0";
    PM_DATA5                          : bit_vector := x"00";
    PM_DATA_SCALE5                    : bit_vector := x"0";
    PM_DATA6                          : bit_vector := x"00";
    PM_DATA_SCALE6                    : bit_vector := x"0";
    PM_DATA7                          : bit_vector := x"00";
    PM_DATA_SCALE7                    : bit_vector := x"0";
    PCIE_GENERIC                      : bit_vector := "000011101111";
    GTP_SEL                           : integer    := 0;
    CFG_VEN_ID                        : std_logic_vector(15 downto 0) := x"10EE";
    CFG_DEV_ID                        : std_logic_vector(15 downto 0) := x"0007";
    CFG_REV_ID                        : std_logic_vector(7 downto 0)  := x"00";
    CFG_SUBSYS_VEN_ID                 : std_logic_vector(15 downto 0) := x"10EE";
    CFG_SUBSYS_ID                     : std_logic_vector(15 downto 0) := x"0007";
    REF_CLK_FREQ                      : integer    := 1
  );
  port (
    -- PCI Express Fabric Interface
    pci_exp_txp             : out std_logic;
    pci_exp_txn             : out std_logic;
    pci_exp_rxp             : in  std_logic;
    pci_exp_rxn             : in  std_logic;

    -- Transaction (TRN) Interface
    trn_lnk_up_n            : out std_logic;

    -- Tx
    trn_td                  : in  std_logic_vector(31 downto 0);
    trn_tsof_n              : in  std_logic;
    trn_teof_n              : in  std_logic;
    trn_tsrc_rdy_n          : in  std_logic;
    trn_tdst_rdy_n          : out std_logic;
    trn_terr_drop_n         : out std_logic;
    trn_tsrc_dsc_n          : in  std_logic;
    trn_terrfwd_n           : in  std_logic;
    trn_tbuf_av             : out std_logic_vector(5 downto 0);
    trn_tstr_n              : in  std_logic;
    trn_tcfg_req_n          : out std_logic;
    trn_tcfg_gnt_n          : in  std_logic;

    -- Rx
    trn_rd                  : out std_logic_vector(31 downto 0);
    trn_rsof_n              : out std_logic;
    trn_reof_n              : out std_logic;
    trn_rsrc_rdy_n          : out std_logic;
    trn_rsrc_dsc_n          : out std_logic;
    trn_rdst_rdy_n          : in  std_logic;
    trn_rerrfwd_n           : out std_logic;
    trn_rnp_ok_n            : in  std_logic;
    trn_rbar_hit_n          : out std_logic_vector(6 downto 0);
    trn_fc_sel              : in  std_logic_vector(2 downto 0);
    trn_fc_nph              : out std_logic_vector(7 downto 0);
    trn_fc_npd              : out std_logic_vector(11 downto 0);
    trn_fc_ph               : out std_logic_vector(7 downto 0);
    trn_fc_pd               : out std_logic_vector(11 downto 0);
    trn_fc_cplh             : out std_logic_vector(7 downto 0);
    trn_fc_cpld             : out std_logic_vector(11 downto 0);

    -- Host (CFG) Interface
    cfg_do                  : out std_logic_vector(31 downto 0);
    cfg_rd_wr_done_n        : out std_logic;
    cfg_dwaddr              : in  std_logic_vector(9 downto 0);
    cfg_rd_en_n             : in  std_logic;
    cfg_err_ur_n            : in  std_logic;
    cfg_err_cor_n           : in  std_logic;
    cfg_err_ecrc_n          : in  std_logic;
    cfg_err_cpl_timeout_n   : in  std_logic;
    cfg_err_cpl_abort_n     : in  std_logic;
    cfg_err_posted_n        : in  std_logic;
    cfg_err_locked_n        : in  std_logic;
    cfg_err_tlp_cpl_header  : in  std_logic_vector(47 downto 0);
    cfg_err_cpl_rdy_n       : out std_logic;
    cfg_interrupt_n         : in  std_logic;
    cfg_interrupt_rdy_n     : out std_logic;
    cfg_interrupt_assert_n  : in  std_logic;
    cfg_interrupt_do        : out std_logic_vector(7 downto 0);
    cfg_interrupt_di        : in  std_logic_vector(7 downto 0);
    cfg_interrupt_mmenable  : out std_logic_vector(2 downto 0);
    cfg_interrupt_msienable : out std_logic;
    cfg_turnoff_ok_n        : in  std_logic;
    cfg_to_turnoff_n        : out std_logic;
    cfg_pm_wake_n           : in  std_logic;
    cfg_pcie_link_state_n   : out std_logic_vector(2 downto 0);
    cfg_trn_pending_n       : in  std_logic;
    cfg_dsn                 : in  std_logic_vector(63 downto 0);
    cfg_bus_number          : out std_logic_vector(7 downto 0);
    cfg_device_number       : out std_logic_vector(4 downto 0);
    cfg_function_number     : out std_logic_vector(2 downto 0);
    cfg_status              : out std_logic_vector(15 downto 0);
    cfg_command             : out std_logic_vector(15 downto 0);
    cfg_dstatus             : out std_logic_vector(15 downto 0);
    cfg_dcommand            : out std_logic_vector(15 downto 0);
    cfg_lstatus             : out std_logic_vector(15 downto 0);
    cfg_lcommand            : out std_logic_vector(15 downto 0);

    -- System Interface
    sys_clk                 : in  std_logic;
    sys_reset_n             : in  std_logic;
    trn_clk                 : out std_logic;
    trn_reset_n             : out std_logic;
    received_hot_reset      : out std_logic
    );
  end component PCIe; 
  
  component PLL125_3
	port
	(-- Clock in ports
	CLK_IN1_P         : in     std_logic;
	CLK_IN1_N         : in     std_logic;
	-- Clock out ports
	CLK_OUT1          : out    std_logic;
	-- Status and control signals
	LOCKED            : out    std_logic
	);
 end component;

begin

  PCIe1 : PCIe
  port map (
    pci_exp_txp             => pci_exp_txp,
    pci_exp_txn             => pci_exp_txn,
    pci_exp_rxp             => pci_exp_rxp,
    pci_exp_rxn             => pci_exp_rxn,
    trn_lnk_up_n            => trn_lnk_up_n,
    trn_td                  => trn_td,                   -- Bus [31 : 0]
    trn_tsof_n              => trn_tsof_n,
    trn_teof_n              => trn_teof_n,
    trn_tsrc_rdy_n          => trn_tsrc_rdy_n,
    trn_tdst_rdy_n          => trn_tdst_rdy_n,
    trn_terr_drop_n         => trn_terr_drop_n,
    trn_tsrc_dsc_n          => trn_tsrc_dsc_n,
    trn_terrfwd_n           => trn_terrfwd_n,
    trn_tbuf_av             => trn_tbuf_av,              -- Bus [31 : 0]
    trn_tstr_n              => trn_tstr_n,
    trn_tcfg_req_n          => trn_tcfg_req_n,
    trn_tcfg_gnt_n          => trn_tcfg_gnt_n,
    trn_rd                  => trn_rd,                   -- Bus [31 : 0]
    trn_rsof_n              => trn_rsof_n,
    trn_reof_n              => trn_reof_n,
    trn_rsrc_rdy_n          => trn_rsrc_rdy_n,
    trn_rsrc_dsc_n          => trn_rsrc_dsc_n,
    trn_rdst_rdy_n          => trn_rdst_rdy_n,
    trn_rerrfwd_n           => trn_rerrfwd_n,
    trn_rnp_ok_n            => trn_rnp_ok_n,
    trn_rbar_hit_n          => trn_rbar_hit_n,           -- Bus [31 : 0]
    trn_fc_sel              => trn_fc_sel,               -- Bus [31 : 0]
    trn_fc_nph              => trn_fc_nph,               -- Bus [31 : 0]
    trn_fc_npd              => trn_fc_npd,               -- Bus [31 : 0]
    trn_fc_ph               => trn_fc_ph,                -- Bus [31 : 0]
    trn_fc_pd               => trn_fc_pd,                -- Bus [31 : 0]
    trn_fc_cplh             => trn_fc_cplh,              -- Bus [31 : 0]
    trn_fc_cpld             => trn_fc_cpld,              -- Bus [31 : 0]
    cfg_do                  => cfg_do,                   -- Bus [31 : 0]
    cfg_rd_wr_done_n        => cfg_rd_wr_done_n,
    cfg_dwaddr              => cfg_dwaddr,               -- Bus [31 : 0]
    cfg_rd_en_n             => cfg_rd_en_n,
    cfg_err_ur_n            => cfg_err_ur_n,
    cfg_err_cor_n           => cfg_err_cor_n,
    cfg_err_ecrc_n          => cfg_err_ecrc_n,
    cfg_err_cpl_timeout_n   => cfg_err_cpl_timeout_n,
    cfg_err_cpl_abort_n     => cfg_err_cpl_abort_n,
    cfg_err_posted_n        => cfg_err_posted_n,
    cfg_err_locked_n        => cfg_err_locked_n,
    cfg_err_tlp_cpl_header  => cfg_err_tlp_cpl_header,   -- Bus [31 : 0]
    cfg_err_cpl_rdy_n       => cfg_err_cpl_rdy_n,
    cfg_interrupt_n         => cfg_interrupt_n,
    cfg_interrupt_rdy_n     => cfg_interrupt_rdy_n,
    cfg_interrupt_assert_n  => cfg_interrupt_assert_n,
    cfg_interrupt_do        => cfg_interrupt_do,         -- Bus [31 : 0]
    cfg_interrupt_di        => cfg_interrupt_di,         -- Bus [31 : 0]
    cfg_interrupt_mmenable  => cfg_interrupt_mmenable,   -- Bus [31 : 0]
    cfg_interrupt_msienable => cfg_interrupt_msienable,
    cfg_turnoff_ok_n        => cfg_turnoff_ok_n,
    cfg_to_turnoff_n        => cfg_to_turnoff_n,
    cfg_pm_wake_n           => cfg_pm_wake_n,
    cfg_pcie_link_state_n   => cfg_pcie_link_state_n,    -- Bus [31 : 0]
    cfg_trn_pending_n       => cfg_trn_pending_n,
    cfg_dsn                 => cfg_dsn,                  -- Bus [31 : 0]
    cfg_bus_number          => cfg_bus_number,           -- Bus [31 : 0]
    cfg_device_number       => cfg_device_number,        -- Bus [31 : 0]
    cfg_function_number     => cfg_function_number,      -- Bus [31 : 0]
    cfg_status              => cfg_status,               -- Bus [31 : 0]
    cfg_command             => cfg_command,              -- Bus [31 : 0]
    cfg_dstatus             => cfg_dstatus,              -- Bus [31 : 0]
    cfg_dcommand            => cfg_dcommand,             -- Bus [31 : 0]
    cfg_lstatus             => cfg_lstatus,              -- Bus [31 : 0]
    cfg_lcommand            => cfg_lcommand,             -- Bus [31 : 0]
    sys_clk                 => clk_125,
    sys_reset_n             => pcie_rst_n,
    trn_clk                 => trn_clk,
    trn_reset_n             => trn_reset_n,
    received_hot_reset      => received_hot_reset
  );


	PCIeIIP1: PCIeIIP PORT MAP(
		mem_wr_we => mem_wr_we,
		mem_wr_data => mem_wr_data,
		mem_wr_addr => mem_wr_addr,
		mem_rd_ce => mem_rd_ce,
		mem_rd_addr => mem_rd_addr,
		mem_rd_data => mem_rd_data,
		mem_clk => mem_clk,
		dma_start => dma_ctrl,
		dma_addr => dma_wr_addr,
		int_dma_enable => tic_int_en,
		trn_clk => trn_clk,
		trn_reset_n => trn_reset_n,
		trn_lnk_up_n => trn_lnk_up_n,
		trn_fc_cplh => trn_fc_cplh,
		trn_fc_cpld => trn_fc_cpld,
		trn_fc_nph => trn_fc_nph,
		trn_fc_npd => trn_fc_npd,
		trn_fc_ph => trn_fc_ph,
		trn_fc_pd => trn_fc_pd,
		trn_fc_sel => trn_fc_sel,
		trn_tbuf_av => trn_tbuf_av,
		trn_tcfg_req_n => trn_tcfg_req_n,
		trn_terr_drop_n => trn_terr_drop_n,
		trn_tdst_rdy_n => trn_tdst_rdy_n,
		trn_td => trn_td,
		trn_tsof_n => trn_tsof_n,
		trn_teof_n => trn_teof_n,
		trn_tsrc_rdy_n => trn_tsrc_rdy_n,
		trn_tsrc_dsc_n => trn_tsrc_dsc_n,
		trn_terrfwd_n => trn_terrfwd_n,
		trn_tstr_n => trn_tstr_n,
		trn_tcfg_gnt_n => trn_tcfg_gnt_n,
		trn_rd => trn_rd,
		trn_rsof_n => trn_rsof_n,
		trn_reof_n => trn_reof_n,
		trn_rsrc_rdy_n => trn_rsrc_rdy_n,
		trn_rsrc_dsc_n => trn_rsrc_dsc_n,
		trn_rerrfwd_n => trn_rerrfwd_n,
		trn_rbar_hit_n => trn_rbar_hit_n,
		trn_rdst_rdy_n => trn_rdst_rdy_n,
		trn_rnp_ok_n => trn_rnp_ok_n,
		cfg_do => cfg_do,
		cfg_rd_wr_done_n => cfg_rd_wr_done_n,
		cfg_dwaddr => cfg_dwaddr,
		cfg_rd_en_n => cfg_rd_en_n,
		cfg_err_ur_n => cfg_err_ur_n,
		cfg_err_cor_n => cfg_err_cor_n,
		cfg_err_ecrc_n => cfg_err_ecrc_n,
		cfg_err_cpl_timeout_n => cfg_err_cpl_timeout_n,
		cfg_err_cpl_abort_n => cfg_err_cpl_abort_n,
		cfg_err_posted_n => cfg_err_posted_n,
		cfg_err_locked_n => cfg_err_locked_n,
		cfg_err_tlp_cpl_header => cfg_err_tlp_cpl_header,
		cfg_err_cpl_rdy_n => cfg_err_cpl_rdy_n,
		cfg_interrupt_rdy_n => cfg_interrupt_rdy_n,
		cfg_interrupt_n => cfg_interrupt_n,
		cfg_interrupt_assert_n => cfg_interrupt_assert_n,
		cfg_interrupt_di => cfg_interrupt_di,
		cfg_interrupt_do => cfg_interrupt_do,
		cfg_interrupt_mmenable => cfg_interrupt_mmenable,
		cfg_interrupt_msienable => cfg_interrupt_msienable,
		cfg_to_turnoff_n => cfg_to_turnoff_n,
		cfg_turnoff_ok_n => cfg_turnoff_ok_n,
		cfg_bus_number => cfg_bus_number,
		cfg_function_number => cfg_function_number,
		cfg_status => cfg_status,
		cfg_command => cfg_command,
		cfg_dstatus => cfg_dstatus,
		cfg_dcommand => cfg_dcommand,
		cfg_lstatus => cfg_lstatus,
		cfg_lcommand => cfg_lcommand,
		cfg_pm_wake_n => cfg_pm_wake_n,
		cfg_pcie_link_state_n => cfg_pcie_link_state_n,
		cfg_trn_pending_n => cfg_trn_pending_n,
		cfg_dsn => cfg_dsn,
		cfg_device_number => cfg_device_number
	);

	cor_top1: cor_top PORT MAP(
		clk_in => clk_20M,
		clk_ctr => mem_clk,
		clkdsp => clk_dsp,
		s1_in => s1_in,
		s2_in => s2_in,
		agc1 => agc1,
		agc2 => agc2,
		clk_adc => clk_adc,
		inmem_addr => mem_wr_addr,
		inmem_we => mem_wr_we,
		inmem_data => mem_wr_data,
		outmem_addr => mem_rd_addr,
		outmem_data => mem_rd_data,
		outmem_ce => mem_rd_ce,
		i2c_status => i2cstatus,
		i2c_control => i2ccontrol,
		tic_out => tic_int,
		pcie_rst_n => pcie_rst_n,
		dma_wr_addr => dma_wr_addr,
		dma_ctrl => dma_ctrl,
		led_1 => led_1,
		led_2 => led_2,
		irq_enable => tic_int_en
	);


	i2c1: i2c_top PORT MAP(
		clk => clk_dsp,
		i2c_control => i2ccontrol, 
		i2c_status => i2cstatus,
		sda => sda,
		scl => scl
	);

  -- clk 100 MHz dif input and 125 MHz PLL 
  PLL1 : PLL125_3
  port map
   (-- Clock in ports
    CLK_IN1_P          => pci_clkp,
    CLK_IN1_N          => pci_clkn,
    -- Clock out ports
    CLK_OUT1           => clk_125,
    -- Status and control signals
    LOCKED             => pll_locked);
	
	-- ExpressCard clk request signal 
	clkreq <= '1';
	pcie_weak <= '0';
	
	-- pcie reset (external signal and PLL)
	pcie_rst_n <= (not(pci_reset) and pll_locked);

end Behavioral;

